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NXP Semiconductors /LPC408x_7x /ETHERNET /RXFILTERWOLCLEAR

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Interpret as RXFILTERWOLCLEAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AUWCLR)AUWCLR 0 (ABWCLR)ABWCLR 0 (AMWCLR)AMWCLR 0 (AUHWCLR)AUHWCLR 0 (AMHWCLR)AMHWCLR 0 (APWCLR)APWCLR 0RESERVED 0 (RFWCLR)RFWCLR 0 (MPWCLR)MPWCLR 0RESERVED

Description

Receive filter WoL clear register.

Fields

AUWCLR

AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
ABWCLR

AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
AMWCLR

AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
AUHWCLR

AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
AMHWCLR

AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
APWCLR

AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
RESERVED

Unused
RFWCLR

RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
MPWCLR

MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
RESERVED

Unused

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data